Calibration of timing mismatch for TIADC based on error table and fractional delay filter

Abstract In this paper, we presents a correcting method based on an error table and fractional delay filter for timing mismatch in time-interleaved analog-to-digital converter (TIADC). This uses the ramp signal to estimate storage value. A Farrow structure is utilized implement calibration of mismatch. Simulation results show that can realize correction suppress spurious component effectively with good effect.